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🚀 Our paper has been accepted at the 19th IEEE International Conference on Software Testing, Verification and Validation (ICST 2026).

📄 𝘛𝘰𝘸𝘢𝘳𝘥 𝘓𝘪𝘷𝘦 𝘕𝘰𝘪𝘴𝘦 𝘍𝘪𝘯𝘨𝘦𝘳𝘱𝘳𝘪𝘯𝘵𝘪𝘯𝘨 𝘧𝘰𝘳 𝘋𝘪𝘴𝘤𝘳𝘦𝘱𝘢𝘯𝘤𝘺 𝘈𝘯𝘢𝘭𝘺𝘴𝘪𝘴 𝘪𝘯 𝘘𝘶𝘢𝘯𝘵𝘶𝘮 𝘚𝘰𝘧𝘵𝘸𝘢𝘳𝘦 𝘌𝘯𝘨𝘪𝘯𝘦𝘦𝘳𝘪𝘯𝘨 🔗 https://lnkd.in/ehw2Mskw

Noise remains a fundamental obstacle to reliable quantum software — yet current models are often static, coarse, and misaligned with real system behaviour.

In this work, we introduce 𝒍𝒊𝒗𝒆 𝒏𝒐𝒊𝒔𝒆 𝒇𝒊𝒏𝒈𝒆𝒓𝒑𝒓𝒊𝒏𝒕𝒊𝒏𝒈, a lightweight and empirical approach to characterising noisy quantum systems.

Our key idea: → leverage 𝒄𝒍𝒂𝒔𝒔𝒊𝒄𝒂𝒍 𝒔𝒉𝒂𝒅𝒐𝒘 𝒕𝒆𝒄𝒉𝒏𝒊𝒒𝒖𝒆𝒔 to build compact, updatable fingerprints of noise → enable efficient comparison of quantum states and platforms (e.g., Qiskit vs Cirq) → support practical workflows for 𝒕𝒆𝒔𝒕𝒊𝒏𝒈, 𝒅𝒆𝒃𝒖𝒈𝒈𝒊𝒏𝒈, and 𝒄𝒓𝒐𝒔𝒔-𝒑𝒍𝒂𝒕𝒇𝒐𝒓𝒎 𝒗𝒂𝒍𝒊𝒅𝒂𝒕𝒊𝒐𝒏

We implement this vision in SIMSHADOW, showing that fingerprints: • capture structured, interpretable noise patterns • reveal systematic cross-platform discrepancies • correlate with observable divergences in program outputs

More broadly, this work bridges 𝒒𝒖𝒂𝒏𝒕𝒖𝒎 𝒊𝒏𝒇𝒐𝒓𝒎𝒂𝒕𝒊𝒐𝒏 𝒕𝒉𝒆𝒐𝒓𝒚 and 𝒔𝒐𝒇𝒕𝒘𝒂𝒓𝒆 𝒕𝒆𝒔𝒕𝒊𝒏𝒈, moving toward more reliable and portable quantum software systems.Faculty of Natural, Mathematical & Engineering SciencesCongratulations Elena, Karine, Sophie, Mohammad!Congratulations, Avner! I hope to see you in Daejeon! 😉 To view or add a comment, sign in Our latest paper was accepted for ICST short papers, vision and emerging result track! 🥳

“Towards Live Noise Fingerprinting for Discrepancy Analysis in Quantum Software Engineering”

            PhD Candidate | Hybrid Quantum–Classical Architectures | Quantum Software Testability | King’s College London
        🚀 Our paper has been accepted at the 19th IEEE International Conference on Software Testing, Verification and Validation (ICST 2026).

Noise remains a fundamental obstacle to reliable quantum software — yet current models are often static, coarse, and misaligned with real system behaviour.

More broadly, this work bridges 𝒒𝒖𝒂𝒏𝒕𝒖𝒎 𝒊𝒏𝒇𝒐𝒓𝒎𝒂𝒕𝒊𝒐𝒏 𝒕𝒉𝒆𝒐𝒓𝒚 and 𝒔𝒐𝒇𝒕𝒘𝒂𝒓𝒆 𝒕𝒆𝒔𝒕𝒊𝒏𝒈, moving toward more reliable and portable quantum software systems. To view or add a comment, sign in New Post: ## Automated Verification of High-Performance Computing (HPC) Kernel Correctness via Dynamic Symbolic Execution & Multi-Modal Model Fusion - Abstract: This paper introduces a novel approach to automatically verify the correctness of computationally intensive kernels within High-Performance Computing (HPC) environments. Leveraging Dynamic Symbolic Execution (DSE) coupled with multi-modal model fusion (combining static code analysis, runtime monitoring, and learned error prediction models), we present a robust verification pipeline capable of detecting elusive corner-case errors that […] To view or add a comment, sign in The delta between an RFC’s mathematical elegance and a carrier-grade network’s operational reality is where the most critical engineering failures—and innovations—occur.

For Senior Network Engineers and Researchers, the transition from theoretical models to field deployment often reveals unforeseen variables: hardware-specific buffer behaviors, non-deterministic latency spikes, and the subtle friction of multi-vendor interoperability. Academic rigor provides the foundation, but empirical field data provides the truth.

At PingDo.net, we recognize that the engineering community needs more than just documentation; it needs a translation layer. Our Theory To Field Map is designed to be that bridge. It serves as a strategic framework for professionals who must reconcile high-level protocol design with the constraints of physical infrastructure. By mapping theoretical expectations against real-world performance metrics, we empower researchers to validate their hypotheses and engineers to harden their deployments with surgical precision.

In this deep dive, we explore how to effectively navigate this transition, ensuring that your network architecture remains resilient when moving from the controlled environment of a lab to the high-pressure demands of a live production stack. We analyze the critical checkpoints where theory often diverges from practice—such as protocol convergence under load and state-table exhaustion—and provide the technical insights necessary to close that loop.

Whether you are optimizing global BGP policies or researching next-generation transport protocols, the ability to map theory to field is what separates a functional network from an optimized one.

Elevate your engineering approach and explore the full framework here: https://lnkd.in/dk8-RpXc 🌐

Join us in redefining the standard for technical precision in the networking community. 📊 To view or add a comment, sign in New Post: Bayesian Program Analysis for Scalable Probabilistic Verification of Timing Constraints in Real‑Time Embedded Systems - — ### Abstract Real‑time embedded systems are increasingly deployed in safety‑critical domains, yet their verification remains a bottleneck due to complex concurrency, deterministic timing requirements, and the combinatorial explosion of state spaces. This paper introduces Bayesian Program Analysis (BPA), a data‑driven approach that automatically learns probabilistic invariants and timing constraints from program execution traces and […] To view or add a comment, sign in

            46 followers
        𝐐𝐮𝐚𝐥𝐜𝐨𝐦𝐦: 𝐄𝐟𝐟𝐢𝐜𝐢𝐞𝐧𝐭 𝐑𝐞𝐚𝐬𝐨𝐧𝐢𝐧𝐠 𝐨𝐧 𝐭𝐡𝐞 𝐄𝐝𝐠𝐞

Deploying complex logic models on resource-constrained edge hardware presents significant challenges due to limited memory and compute power.

A new framework addresses these limitations through Low-Rank Adaptation (LoRA) and budget-forced reinforcement learning. By training models to produce shorter responses without sacrificing accuracy, the system reduces computational overhead during inference.

Further optimizations include parallel test-time scaling and a dynamic adapter-switching mechanism. This approach specifically targets memory-bound decoding phases and overall latency, making it feasible to run sophisticated reasoning tasks on mobile or embedded devices.

The implementation focuses on balancing model performance with hardware constraints, ensuring that intelligence remains accessible without requiring high-end server infrastructure.

            646,005 followers
        What does the current quantum software stack look like? Sara A. Metwalli shares the view from the forefront of this rapidly evolving field.
    To view or add a comment, sign in
Model checkers can uncover hard-to-find requirement violation scenarios, but steering them to find all substantially distinct ones in a fault-tolerant system's high-level design can be challenging in practice. Check out our paper recently published in Empirical Software Engineering, if you want to learn how our systematic exploration process can help: https://rdcu.be/eYfrs. 
    To view or add a comment, sign in

            53 followers
        A new paper about a multi-year industrial case study with the thyssenkrupp competence center in Budapest about using formal verification in the automotive industry.
            Research Assistant at Budapest University of Technology and Economics
        Model checkers can uncover hard-to-find requirement violation scenarios, but steering them to find all substantially distinct ones in a fault-tolerant system's high-level design can be challenging in practice. Check out our paper recently published in Empirical Software Engineering, if you want to learn how our systematic exploration process can help: https://rdcu.be/eYfrs. 
    To view or add a comment, sign in

            9,293 followers
        ParityQC is proud to provide the Architecture/System Layer to the German Quantum Software Stack.

FullStaQD marks a significant step forward for quantum computing in Germany. The collaborative effort brings together leading partners from industry and academia to create a fully open-source reference architecture and reference implementation of quantum software stack. 🇩🇪🇪🇺

At ParityQC, we’re proud to be leading the “System Layer,” building an HPC-compatible quantum architecture infrastructure that will unlock the full potential of quantum computers across different hardware platforms with our world leading Parity Twine method based on the ParityQC Architecture.

The kick-off of our System Layer working package was inspiring. With insightful technical deep dives into Quantum Compilers (ParityQC), Quantum Runtimes (Technische Universität München), Qrisp (Fraunhofer FOKUS) and Quantum HPC integration (Technische Universität München), we could truly feel the determination of all partners to solve the hard problems of a quantum software stack hands-on and deliver a real, impactful solution.

ParityQC is committed to strengthen the German and European quantum ecosystem. We believe in collaborative innovation and empowering a new generation of quantum developers across the whole quantum stack.

Let’s build the future of quantum, together! Bundesdruckerei GmbH, DB Systel GmbH, eleQtron GmbH, Fraunhofer FOKUS, Fraunhofer IAO, FZI Forschungszentrum Informatik, Kipu Quantum, Karlsruher Institut für Technologie (KIT), ParityQC, Technische Universität München

#quantumcomputing #FullStaQD #opensource #ParityQC #quantumtechnology #Europe #innovation #quantumecosystem #ParityQCArchitecture #ParityTwine To view or add a comment, sign in

            3,381 followers
        We're excited to participate in the upcoming Conference on Systems Engineering Research (CSER) in Arlington, VA, where our team will be demonstrating the Tom Sawyer SysML v2 Viewer and joining discussions around the evolving SysML v2 specification.

This year’s theme, Intelligent Digital Twin-enabled Systems Engineering for 21st Century Sociotechnical Systems, reflects exactly the kind of complex, model-driven challenges our SysML v2 Viewer is built to support.

We look forward to connecting with the systems engineering research community and contributing to the conversations shaping the next generation of model-based systems engineering.

#CSER2026 #SysMLv2 #MBSE #SystemsEngineering #DigitalEngineering #TomSawyerSoftware To view or add a comment, sign in

        649 followers
      
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